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EM250
4.11.3 Internal RC Oscillator
The EM250 has a low-power, low-frequency RC oscillator that runs all the time. Its nominal frequency is
10kHz.
The RC oscillator has a coarse analog trim control, which is first adjusted to get the frequency as close to
10kHz as possible. This raw clock is used by the chip management block. It is also divided down to 1kHz using
a variable divider to allow software to accurately calibrate it. This calibrated clock is available to the sleep
timer.
Timekeeping accuracy depends on temperature fluctuations the chip is exposed to, power supply impedance,
and the calibration interval, but in general it will be better than 150ppm (including crystal error of 40ppm). If
this tolerance is accurate enough for the application, then there is no need to use an external 32.768kHz
crystal oscillator. By removing the 32.768kHz oscillator, the external component count further decreases as
does the Bill of Material cost.
Note:
If the 32.768kHz crystal is not needed, then OSC32A and OSC32B pins should be left open or not
connected.
Table 14 lists the specifications of the RC oscillator.
Table 14. RC Oscillator Specifications
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Frequency
Analog trim steps
10
1
kHz
kHz
Frequency variation with supply
For a voltage drop from 3.6V to 3.1V or 2.6V
0.75
1.5
%
to 2.1V
4.12 Random Number Generator
The EM250 allows for the generation of random numbers by exposing a randomly generated bit from the RX
ADC. Analog noise current is passed through the RX path, sampled by the receive ADC, and stored in a
register. The value contained in this register could be used to seed a software-generated random number. The
EmberZNet PRO stack utilizes these random numbers to seed the Random MAC Backoff and Encryption Key
Generators.
4.13 Watchdog Timer
The EM250 contains a watchdog timer clocked from the internal oscillator. The watchdog is disabled by
default, but can be enabled or disabled by software.
If the timer reaches its time-out value of approximately 2 seconds, it will generate a reset signal to the chip.
When software is running properly, the application can periodically restart this timer to prevent the reset
signal from being generated.
The watchdog will generate a low watermark interrupt in advance of actually resetting the chip. This low
watermark interrupt occurs approximately 1.75 seconds after the timer has been restarted. This interrupt can
be used to assist during application debug.
Page 25
120-0082-000V Rev 1.1
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